Online

Erturk, Mete

Electrical Engineering

2008

PhD

In the last decade, wireless network routers, multi-media devices with Bluetooth© or similar communication capabilities, mobile cell-phones, and other "RF" devices have found widespread use in the consumer market. The integration and cost advantages of CMOS-only chips have attracted circuit designers in academia and industry, and CMOS technology is now a strong contender along with BiCMOS, and 111-V semiconductors for analog 1 mixed signal and radio frequency applications. RF CMOS technology has numerous advantages that come with the feasibility of system-on-chip. These advantages include reduced fabrication cost and reduced pin count due to die sharing between analog and digital portions. Perhaps the most critical disadvantage of RF CMOS is the very high l/f noise levels observed in MOSFETs in comparison to BJTs (bipolar-junction transistor). The silicon - silicondioxide interface is crucial to the operation of all MOSFETs, and unlike bipolar devices, MOSFETs are largely surface conductive devices, with device current flowing at or near the interface.
This leads to the large l/f noise associated with FETs. There has been on-going research to study the physical mechanism of l/f noise. The compact models used to predict device noise in circuit simulations have also been improved. It has recently been observed that llf noise increases during the lifetime of a transistor. Also, large statistical variations in noise level have been reported. The existing models fail to explain such variability in l/f noise. The work presented here extends the state-ofthe art of l/f noise modeling through experimental and theoretical analysis of noise reliability and statistics. A new model is developed based on a novel theory that investigates the relationship between the spatial profile of interface traps and the bias dependence of l/f noise. The theory is tested against device noise measurements, as well as RF circuit phase noise measurements.