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Sulley, Raphael K.

Electrical and Computer Engineering

2006

PhD

The continuous and aggressive dimensional miniaturization of the conventional MOSFET has been the main impetus for the vast growth of the IC industry over the past several decades. As MOSFET scaling approaches fundamental physical limits, novel device architectures are required in order to enable the ultimate in scaling device dimensions and to maintain the performance gain expected from scaling. One of these novel devices, which is a strong candidate to succeed the conventional planar device, is the double-gate FinFET. This dissertation investigates the temperature dependency of threshold voltage (dVth/dT) and subthreshold characteristics (dS/dT) of the double-gate FinFET. The temperature dependence of the threshold voltage is a very important parameter for device design; the threshold voltage shift due to self-heating or environmental temperature variations must be considered in the design phase of circuits and products. The expressions are developed for the surface potential and the threshold voltage including the presence of increased interface trap density (D[subscript it]) inherent to the <110> sidewall. This dissertation examines the effects of temperature between 218K and 393K of FinFET operation in weak inversion. The threshold voltage and subthreshold swing of fully-depleted and partially-depleted double-gate n-type FinFETs are analyzed and compared to theoretical predictions. The theoretical model of the temperature coefficient of threshold voltage is modified to confirm the validity of the experimental results of the FinFET. The dissertation also examines the scaling effects on the temperature coefficient of the threshold voltage of the MOSFET. We observe that the temperature coefficient of the threshold voltage of MOSFET decreases with scaling and approaches the temperature coefficient of the threshold voltage of a fully-depleted device.