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Craig, Jesse

Computer Science

2006

MS

The growing complexity of function and gate counts found in modern digital semiconductor designs has made the verification of those designs the dominant cost of their development and implementation. Design teams rarely have the resources to exhaustively verify their designs, leading to a growing number of bugs not found during the verification process. This thesis will study a popular technique for verifying digital designs, directed random verification, and the diminishing returns which are often cited as the technique's greatest challenge. This thesis shows that these diminishing returns are directly related to the inherent redundancy found in directed random verification and explores a method of reducing this redundancy. The method of optimization creates checkpoints at user selected, randomly controlled, decision points and exhaustively explores the outcomes of these decision points. This method is facilitated by a new software system, the Reduction of Redundancy (RoR) Verification System, introduced in this thesis. Using this software system several verification environments were created to understand the method's effects on the verification performance and the challenges with implementing the method in a verification environment. In each case the optimization method is able to increase the performance of the verification environment with only a minimal amount of effort by the verification engineer.