Memory design plays an important role in modern computer technology in regard to overall performance and reliability. Prior memory technologies, including magneticcore memory, hard disk drives, DRAM, SRAM have limitations in regard to bit density, IC integration, power efficiency, and physical size, respectively. To address these limitations we propose to develop a magnetic graphene random access memory (MGRAM) utilizing graphene Hall effect, which takes advantage of the inherent reliability of magnetic memory and superior electrical properties of graphene (high carrier mobility, zero-band gap, high Hall sensitivity). As the graphene magnetic memory device will be integrated with a CMOS ASIC design an analog circuit model for the MGRAM cell is necessary and important. In this study the electrical circuit model is developed utilizing the analog circuit modeling language Verilog-A. The electrical circuit model characterizes the graphene electrical properties and the ferromagnetic core magnetic properties that retains the bit-state value. MGRAM device simulations studying varying coil width, height, radius, contact pad configuration, graphene shape, is performed with the MagOasis Magsimus tool to evaluate the device performance. Model results show a maximum Hall effect voltage of 100mV for a bias current of 50uA with a 1 Tesla magnetic field, and a writing speed of 6-9ns for setting the magnetic state. These results will be validated against the circuit hardware measurement and will be used for model refinement.